/*
 * @[H]:  Copyright (c) 2021 Phytium Information Technology, Inc. 
 * 
 *  SPDX-License-Identifier: Apache-2.0. 
 * 
 * @Date: 2021-07-19 14:46:01
 * @LastEditTime: 2021-07-19 18:22:24
 * @Description:  Description of file
 * @Modify History: 
 * * * Ver   Who        Date         Changes
 * * ----- ------     --------    --------------------------------------
 */

#include "f_xmac_hw.h"

void FXmacResetHw(u32 base_address)
{
    u32 reg_value;

    // Disable the interrupts
    FXMAC_WRITEREG32(base_address, FXMAC_IDR_OFFSET, FXMAC_IXR_ALL_MASK);

    // Stop transmission,disable loopback and Stop tx and Rx engines
    reg_value = FXMAC_READREG32(base_address, FXMAC_NWCTRL_OFFSET);
    reg_value &= ~((u32)FXMAC_NWCTRL_TXEN_MASK |
                   (u32)FXMAC_NWCTRL_RXEN_MASK);

    // Clear the stats registers
    reg_value |= FXMAC_NWCTRL_STATINC_MASK;
    FXMAC_WRITEREG32(base_address, FXMAC_IDR_OFFSET, reg_value);

    // Clear all status flags
    FXMAC_WRITEREG32(base_address, FXMAC_TXSR_OFFSET, -1);
    FXMAC_WRITEREG32(base_address, FXMAC_RXSR_OFFSET, -1);
    /* Clear the interrupt status */
    FXMAC_WRITEREG32(base_address, FXMAC_ISR_OFFSET, FXMAC_IXR_ALL_MASK);

    /* Clear the tx base address */
    FXMAC_WRITEREG32(base_address, FXMAC_TXQBASE_OFFSET, 0x0U);
    /* Clear the rx base address */
    FXMAC_WRITEREG32(base_address, FXMAC_RXQBASE_OFFSET, 0x0U);
    /* Update the network config register with reset value */
    FXMAC_WRITEREG32(base_address, FXMAC_NWCFG_OFFSET, FXMAC_NWCFG_RESET_MASK);
    // Update the hash address registers with reset value
    FXMAC_WRITEREG32(base_address, FXMAC_HASHL_OFFSET, 0);
    FXMAC_WRITEREG32(base_address, FXMAC_HASHH_OFFSET, 0);
}